Memory cells of a flash memory array are based on trapping of charge carriers in a floating gate or in a dielectric memory layer confined by thin confinement layers, e.g., an ONO-layer sequence. These non-volatile memory cells are electrically programmable and erasable.
One cell concept has been developed to allow for the storage of two bits per cell. Therein, a wordline crossing an active substrate and provided with an ONO-layer sequence is designed to charge-trap channel hot electrons (CHE) in confined regions of the ONO-layer sequence on both sides of a channel or depletion region in the substrate. In other words the charge carriers are trapped in a location of the ONO-layer sequence sandwiched between the word line (or gate electrode) and the active substrate, where separated source and drain regions, the depletion region and the gate electrode approach each other.
Charge carriers moving from source to drain through the channel or depletion region are accelerated and gain enough energy in order to penetrate through the lower confinement layer of the ONO-layer sequence. These charge carriers are then trapped within the memory layer. As a result, the trapped charge carriers influence the threshold voltage of the cell transistor structure. Different programming states can then be read by applying the appropriate reading voltages.
In consequence, programming and reading occurs by means of applying different voltages to each two bitlines connecting opposite source and drain regions of a transistor. Which of the two locations per cell is read out with respect to the stored charge carriers depends on the current direction according to the voltage drop between the two bitlines.
In one embodiment of a semiconductor flash memory, memory cells are arranged within an array 2 at cross-points of word lines 14 with bit lines 10, 12 as shown in FIG. 1. Each memory cell has a transistor 16 with source and drain regions 11, 13 (see FIG. 2). Reference numeral 10 in this embodiment refers to bit lines connecting source regions 11, and numeral 12 denotes bit lines connected with drain regions. In the architecture of this embodiment, e.g., erase operations are performed collectively and simultaneously with respect to multiple memory cells arranged in a so-called e-sector (erase sector) 19 or 21, wherein an e-sector is defined by control units 18, 20 associated with a dedicated set of word lines. An e-sector is the smallest possible segment of an array to perform the task of erasing bits.
When erasing bit information stored in the memory cells, a considerable voltage of, e.g., −7 V is applied to all the word lines 14 of an e-sector (e-sector 21 in FIG. 1). At the same time a large voltage of, e.g., +6 V is applied to the bit lines 10 and 12 in order to generate hot holes, which compensate for the electrons stored in the memory layer when being injected therein.
One problem that may arise due to such architectures is that memory cells associated with word lines 14 of a neighboring e-sector 19 undergo the same voltage difference with respect to source and drain as those cells located within the currently active e-sector 21, because these are connected with the same bit lines 10 or 12.
FIG. 2 shows a cross section of two field effect transistors 16 of respective two-bit memory cells, which neighbor each other. The memory cells are accessed via respective word lines 14a, 14b, which form the outermost word lines of a corresponding e-section 19, 21. Word line 14b (gate electrode) of the memory cell within the e-sector 21 is provided with a voltage of −7 V and drain bit line 12 is provided with a voltage of +6 V.
As a result, an electron-hole pair is generated (band-to-band tunneling). The electron moves towards the large drain potential. The hole gains energy and drifts towards the negative gate electrode potential and is eventually injected into the ONO-layer in order to erase the bit content stored therein as it is desired.
However, due to the large an amount of holes thus generated some holes may also be accelerated vertically down towards the substrate (well). Secondary electrons may be generated there by means of impact ionization. These secondary electrons are attracted by gate electrode (word line 14a) currently supplied with a voltage of +4 V and not being intended to be erased. If the secondary electrons equally gain sufficient energy, they may even enter the memory layer and thus program a hitherto non-programmed memory cell (bits #1 or #2 of the neighboring memory cell) despite the extraordinarily large voltage of +6 V supplied to the drain region 13 located between the gate electrodes. Note, a voltage of +3 V or +4 V (instead of, e.g., zero voltage) may be applied to word lines 14 of neighboring e-sectors in order to inhibit unintended erasure of programmed bits (inhibit voltage).
Further, as shown in FIG. 2, an electron-hole pair may also be generated by impact ionization at the pn-junction at the bottom of drain region 13, which is connected to bit line 12, due a generally strong gradient of free charge carrier concentration. The same effect of unintended programming of unprogrammed bits due to hot electrons may happen as described above.
Moreover, in excess of what happens with respect to neighboring word lines of different e-sectors as described above, the electron-hole pair generation at the bottom pn-junction of the drain region may affect each word line of a neighboring (inhibited) e-sector. The effect of undesired programming of bits during an erase is known as a bit line disturb.
As is further shown in FIG. 2, source regions 11 connected to non-selected bit lines 10 may be supplied with a voltage of 4 V, which is accomplished by means of so-called shunt transistors. The goal is to reduce unintended programming of erased bits due to the injection of channel hot electrons.
Hence, there is a need to improve a semiconductor flash memory particularly with regard to the performance characteristics during erase operations. Further, the lifetime (number of write and erase cycles) of a semiconductor flash memory product should be increased.